The present invention relates to complementary metal oxide semiconductor (CMOS) compact static random access memory (SRAM) cell layouts for implementing one-port and two-port operation.
FIG. 1 illustrates a conventional six-device SRAM cell including a single word line. The prior art six-device SRAM cell includes four N-channel field effect transistors (NFETs) N1, N2, N3, N4 and two P-channel field effect transistors (PFETs) P5, P6. SRAM storage cell includes a pair of inverters formed by PFET P5 and NFET N2 and PFET P6 and NFET N3 that operate together in a loop to store a bit value. PFET P5 and NFET N2 and PFET P6 and NFET N3 are respectively connected between a voltage supply rail VDD and ground GND. The true bitline BLT is connected by NFET N1 to the drain and source connection of PFET P5 and NFET N2 and to the gate input to the inverter PFET P6 and NFET N3 at net C. The compliment bitline BLC is connected by NFET N4 to the drain and source connection of PFET P6 and NFET N3 and to the gate input to the inverter PFET P5 and NFET N2 at net T. The WORDLINE provides the gate input to wordline NFETs N1 and N4. The WORDLINE is activated, turning on wordline NFETs N1 and N4, to perform a read or write operation.
FIG. 2 illustrates another six-device SRAM cell with the wordline connection separated into two wordlines WORDLINE 0, WORDLINE 1, enabling separated single ended read operations to be performed with a conventional six-device SRAM cell.
For example, U.S. Pat. No. 5,815,432 discloses a single-ended read, dual-ended write dual port SRAM cell.
FIGS. 3A and 3B generally illustrate not shown to scale a prior art cell layout for the six-device SRAM cell of FIG. 1. Each of the SRAM devices NFETs N1, N2, N3, N4 and PFETs P5, P6 is respectively indicated within a solid line box. First level metal is indicated by M1, diffusion is indicated by RX and polysilicon is indicated by PC. A metal local interconnect is indicated by MC. A metal contact that extends between the first level metal M1 and local interconnect MC is indicated by CA.
In FIG. 3A, the true and compliment bitlines BLT, BLC are indicated respectively within dashed lines at the top of the SRAM cell, as shown in FIG. 3A. Voltage supply rail VDD and ground GND are indicated respectively near the bottom and center of the SRAM cell. Storage cell nets C and T are generally indicated. Wordline FETs N1 and N4 respectively are formed below the true and compliment bitlines BLT, BLC and share a common polysilicon PC WORDLINE connection. NFETs N2 and N3 are formed near the middle of the SRAM cell and PFETs P5 and P6 are formed below NFETs N2 and N3 closer to the bottom of the SRAM cell. NFET N2 and PFET P5 share a common polysilicon (PC) connection. NFET N3 and PFET P6 share a common polysilicon (PC) connection. Both wordline NFETs N1 and N4 are formed having width extending in a horizontal or X direction and length extending in a vertical or Y direction, as shown in the orientation of FIG. 3A. NFETs N2 and N3 and PFETs P5 and P6 are not formed in the same direction as the wordline NFETs N1 and N4. NFETs N2 and N3 and PFETs P5 and P6 have a width extending in the vertical or Y direction and length extending in the horizontal or X direction. Wordline NFETs N1 and N4 are oriented 90xc2x0 offset from the rest of the devices NFETs N2 and N3 and PFETs P5 and P6. In FIG. 3B, the first and second level metals M1, M2 are separately shown together with contacts CA.
A disadvantage of the prior art cell layout of FIGS. 3A and 3B for the six-device SRAM cell is the area required to form the SRAM cell. There are many applications where being able to have two read operations in a static random access memory (SRAM) is desirable. The prior art cell layout of FIGS. 3A and 3B is very difficult to arrange such that a two-port configuration is possible. For example, the overhead for adding an additional port to the traditional SRAM cell as illustrated in FIGS. 3A and 3B typically doubles the cell area. Another disadvantage of the prior art cell layout of FIGS. 3A and 3B is that the all the devices NFETs N1, N2, N3, N4 and PFETs P5, P6 do not extend in the same direction. As a result, device matching is more difficult.
U.S. Pat. No. 5,930,163 discloses an SRAM cell including P-well and N-well regions where inverters constituting an SRAM cell are formed. The P-well region is divided into two parts, which are laid out on the two sides of the N-well region. Boundaries (BL11, BL12) are formed to run parallel to bit lines (BL, /BL). With this layout, diffusion layers (ND1, ND2) within the P-well regions can be formed into simple shapes free from any bent portion, reducing the cell area. In this layout all the cell devices extend in the same direction. However, this layout is limited by a minimum required contact-to-contact spacing between contacts.
Referring also to FIG. 6A, a prior art interconnect structure of a six-device SRAM cell including a first metal layer METAL 1, and a pair of contacts CA with one contact CA connecting the first metal layer METAL 1 to a diffusion RX layer and another contact CA connecting the first metal layer METAL 1 to a polysilicon PC layer. An arrow labeled D indicates a minimum required contact-to-contact spacing between contacts. This required contact-to-contact spacing D limits how closely devices can be provided in the SRAM cell layout of U.S. Pat. No. 5,930,163.
A need exists for compact SRAM cell layouts for implementing one-port and two-port operation. It is also desirable that all the devices NFETs N1, N2, N3, N4 and PFETs P5, P6 extend in the same direction to insure effective device matching.
Principal objects of the present invention are to provide compact SRAM cell layouts for implementing one-port and two-port operation. Other important objects of the present invention are to provide such compact SRAM cell layouts that effectively insure device matching with all SRAM devices extending in the same direction; and to provide such compact SRAM cell layouts substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, compact static random access memory (SRAM) cell layouts are provided for implementing one-port and two-port operation. The SRAM cell layouts include a plurality of field effect transistors (FETs). The plurality of FETs defines a storage cell and a pair of wordline FETs coupled to the storage cell. Each of the plurality of FETs has a device structure extending in a single direction. The device structure of each of the plurality of FETs includes a diffusion layer, a polysilicon layer and first metal layer. A local interconnect connects the diffusion layer, the polysilicon layer and the first metal layer. Each of the pair of wordline FETs having a gate input connected to a wordline. The wordline including a single wordline for implementing one-port operation or two separate wordline connections for implementing two-port operation.
In accordance with features of the invention, the local interconnect includes a metal local interconnect that lays on the diffusion and polysilicon layers for electrically connecting diffusion and polysilicon layers and a metal contact that extends between the metal local interconnect and the first level metal for electrically connecting diffusion and polysilicon layers and the first level metal. Alternatively, a metal contact lays on the diffusion and polysilicon layers for electrically connecting diffusion and polysilicon layers and the first level metal. The local interconnect further includes a conduction layer disposed on a butted diffusion connection of diffusion-p type and diffusion-n type and a metal local interconnect disposed on the conduction layer.